----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:44:02 07/16/2008 
-- Design Name: 
-- Module Name:    ac97_wrapper - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Top level PARTIAL RECONFIGURABLE entity
--
-- Dependencies: 
--
-- Revision: 
-- Revision 1.00a
-- 			2.00a - changed direction of the FFT and data flow
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.busmacro_xc2vp_pkg.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ac97_wrapper is
  port (
    clk				: in std_logic;
    reset_button	: in std_logic;
    
	 Debug 			: out std_logic_vector(3 downto 0);
	 LED_0			: out std_logic;
	 LED_1			: out std_logic;
	 LED_2			: out std_logic;
	 LED_3			: out std_logic;
	 SW_0				: in std_logic;
	 SW_1				: in std_logic;
	 SW_2				: in std_logic;
	 SW_3				: in std_logic;
	 PB_DOWN			: in std_logic;
	 PB_UP			: in std_logic;
	 PB_LEFT			: in std_logic;
	 PB_RIGHT		: in std_logic;
	 
	 KBD_CLOCK		: in std_logic;
	 KBD_DATA		: in std_logic;
	 
	 VGA_OUT_RED : out  STD_LOGIC_VECTOR (7 downto 0);
	 VGA_OUT_GREEN : out  STD_LOGIC_VECTOR (7 downto 0);
	 VGA_OUT_BLUE : out  STD_LOGIC_VECTOR (7 downto 0);
	 VGA_OUT_PIXEL_CLOCK : out  STD_LOGIC;
	 VGA_COMP_SYNCH : out  STD_LOGIC;
	 VGA_OUT_BLANK_Z : out  STD_LOGIC;
	 VGA_HSYNCH : out  STD_LOGIC;
	 VGA_VSYNCH : out  STD_LOGIC;
	 
    AC97reset_n	: out std_logic;        -- AC97Clk
    AC97Clk   		: in  std_logic;
    sync      		: out std_logic;
    SData_Out 		: out std_logic;
    SData_In  		: in  std_logic

    );
end ac97_wrapper;

architecture structural of ac97_wrapper is

component BUFG is
	port ( 	I : in std_logic;
				O : out std_logic);
end component BUFG;

component reset_module is
    Port ( 	reset_button : in  STD_LOGIC;
				locked_48k : in std_logic;
				locked_40M : in std_logic;
				reset : out  STD_LOGIC;
				hard_reset : out  STD_LOGIC);
end component reset_module;

component generate_48k_clk is
    Port ( AC97_Bit_Clk : in  STD_LOGIC;
           reset 			: in  STD_LOGIC;
			  sync			: in 	std_logic;
           clk_48k		: out  STD_LOGIC;
			  locked_48k	: out std_logic;
			  status			: out std_logic);
end component generate_48k_clk;

COMPONENT DCM_40
PORT(
	CLKIN_IN : IN std_logic;
	RST_IN : IN std_logic;          
	CLKFX_OUT : OUT std_logic;
	CLK0_OUT : OUT std_logic;
	LOCKED_OUT : OUT std_logic
	);
END COMPONENT;

component keyboard_control is
    Port ( 	clk : in std_logic;
				reset : in  STD_LOGIC;
				
				KBD_CLOCK : in  STD_LOGIC;
				KBD_DATA : in  STD_LOGIC;
				
				debug	: out std_logic_vector(3 downto 0);
				
				key_out	:	out std_logic_vector(7 downto 0);
				key_valid: out std_logic;
				
				main_control	: out std_logic_vector(7 downto 0);
				time_control	: out std_logic_vector(7 downto 0);
				freq_control	: out std_logic_vector(7 downto 0));
end component keyboard_control;

component ac97_if is
port (
    ClkIn 					: in std_logic;
    Reset 					: in std_logic;
    
    -- All signals synchronous to clk
    PCM_Playback_Left	: in std_logic_vector(15 downto 0);
    PCM_Playback_Right	: in std_logic_vector(15 downto 0);
    PCM_Playback_Accept	: out std_logic;
    
    PCM_Record_Left		: out std_logic_vector(15 downto 0);
    PCM_Record_Right		: out std_logic_vector(15 downto 0);
    PCM_Record_Valid		: out std_logic;

    Debug 					: out std_logic_Vector(3 downto 0);
	 LED_0					: out std_logic;
	 LED_1					: out std_logic;
	 LED_2					: out std_logic;
	 LED_3					: out std_logic;
    
    AC97reset_n 			: out std_logic;        -- AC97Clk
    AC97Clk   				: in  std_logic;
    sync      				: out std_logic;
    SData_Out 				: out std_logic;
    SData_In  				: in  std_logic
    );

end component;

component PRM_time_1 is
port (
	clk 						: in std_logic;
	clk_48k					: in std_logic;
	reset 					: in std_logic;
	
	control_in 				: in std_logic_vector(7 downto 0);
	control_out				: out std_logic_vector(3 downto 0);
	
	PCM_data_in_right 	: in std_logic_vector(15 downto 0);
	PCM_data_in_left 		: in std_logic_vector(15 downto 0);
	PCM_data_out_right 	: out std_logic_vector(15 downto 0);
	PCM_data_out_left 	: out std_logic_vector(15 downto 0)
	);
end component PRM_time_1;

component PRM_freq_1 is
port (
	clk_100M					: in std_logic;
	clk_48k					: in std_logic;
	reset 					: in std_logic;
	
	control_in 				: in std_logic_vector(15 downto 0);
	control_out				: out std_logic_vector(3 downto 0);
	
	fft_data_in_re		 	: in std_logic_vector(23 downto 0);
	fft_data_in_im 		: in std_logic_vector(23 downto 0);
	fft_data_out_re 		: out std_logic_vector(23 downto 0);
	fft_data_out_im	 	: out std_logic_vector(23 downto 0)
	);
end component PRM_freq_1;

component full_fft is
    Port (	clk_100M : in  STD_LOGIC;
				clk_48k : in std_logic;
				reset : in  STD_LOGIC;
			  
				fwd_inv : in std_logic;
				enable : in std_logic;
			  
				x0_re : in  STD_LOGIC_VECTOR (23 downto 0);
				x0_im : in  STD_LOGIC_VECTOR (23 downto 0);
				y0_re : out  STD_LOGIC_VECTOR (23 downto 0);
				y0_im : out  STD_LOGIC_VECTOR (23 downto 0);
		   
				done : out std_logic;
		   
				sample_number : out std_logic_vector(7 downto 0));
end component full_fft;

component VGA_controller is
    Port ( 	clk_40M : in  STD_LOGIC;
				clk_48k: in std_logic;
				reset : in  STD_LOGIC;
			  
				time_control_out		: in std_logic_vector(3 downto 0);
				freq_control_out		: in std_logic_vector(3 downto 0);
				main_control_in			: in std_logic_vector(7 downto 0);
				time_control_in			: in std_logic_vector(7 downto 0);
				freq_control_in			: in std_logic_vector(7 downto 0);
				keyboard_control_data	: in std_logic_vector(7 downto 0);
				keyboard_data_valid		: in std_logic;
				
				fft_data_re_in_left_0	: in std_logic_vector(23 downto 0);
				fft_data_im_in_left_0	: in std_logic_vector(23 downto 0);
				fft_data_re_in_left_1	: in std_logic_vector(23 downto 0);
				fft_data_im_in_left_1	: in std_logic_vector(23 downto 0);
				fft_data_re_in_left_2	: in std_logic_vector(23 downto 0);
				fft_data_im_in_left_2	: in std_logic_vector(23 downto 0);
				
				sample_number				: in std_logic_vector(6 downto 0);
		   
				VGA_OUT_RED : out  STD_LOGIC_VECTOR (7 downto 0);
				VGA_OUT_GREEN : out  STD_LOGIC_VECTOR (7 downto 0);
				VGA_OUT_BLUE : out  STD_LOGIC_VECTOR (7 downto 0);
				VGA_OUT_PIXEL_CLOCK : out  STD_LOGIC;
				VGA_COMP_SYNCH : out  STD_LOGIC;
				VGA_OUT_BLANK_Z : out  STD_LOGIC;
				VGA_HSYNCH : out  STD_LOGIC;
				VGA_VSYNCH : out  STD_LOGIC
				);
end component VGA_controller;

component busmacro_xc2vp_l2r_async_enable_narrow is		
port (
	input0 : in std_logic;
	input1 : in std_logic;
	input2 : in std_logic;
	input3 : in std_logic;
	input4 : in std_logic;
	input5 : in std_logic;
	input6 : in std_logic;
	input7 : in std_logic;
	enable0 : in std_logic;
	enable1 : in std_logic;
	enable2 : in std_logic;
	enable3 : in std_logic;
	enable4 : in std_logic;
	enable5 : in std_logic;
	enable6 : in std_logic;
	enable7 : in std_logic;
	output0 : out std_logic;
	output1 : out std_logic;
	output2 : out std_logic;
	output3 : out std_logic;
	output4 : out std_logic;
	output5 : out std_logic;
	output6 : out std_logic;
	output7 : out std_logic
	);
end component;


component busmacro_xc2vp_r2l_async_enable_narrow is
port (
	input0 : in std_logic;
	input1 : in std_logic;
	input2 : in std_logic;
	input3 : in std_logic;
	input4 : in std_logic;
	input5 : in std_logic;
	input6 : in std_logic;
	input7 : in std_logic;
	enable0 : in std_logic;
	enable1 : in std_logic;
	enable2 : in std_logic;
	enable3 : in std_logic;
	enable4 : in std_logic;
	enable5 : in std_logic;
	enable6 : in std_logic;
	enable7 : in std_logic;
	output0 : out std_logic;
	output1 : out std_logic;
	output2 : out std_logic;
	output3 : out std_logic;
	output4 : out std_logic;
	output5 : out std_logic;
	output6 : out std_logic;
	output7 : out std_logic
	);
end component;

	signal clk_100M					: std_logic := '0';
	signal reset						: std_logic := '0';
	signal hard_reset					: std_logic := '0';
	signal hard_reset_n				: std_logic := '0';

	signal key_debug					: std_logic_vector(3 downto 0) 	:= (others => '0');
	signal key_out						: std_logic_vector(7 downto 0)	:= (others => '0');
	signal key_valid					: std_logic	:= '0';
	signal fft_control_keyboard	: std_logic_vector(7 downto 0)	:= (others => '0');
	signal main_control_keyboard	: std_logic_vector(7 downto 0)	:= (others => '0');

	signal PCM_PR_to_BM_Left		: std_logic_vector(15 downto 0)	:= (others => '0');
	signal PCM_PR_to_BM_Right		: std_logic_vector(15 downto 0)	:= (others => '0');
	signal PCM_BM_to_PR_Left		: std_logic_vector(15 downto 0)	:= (others => '0');
	signal PCM_BM_to_PR_Right		: std_logic_vector(15 downto 0)	:= (others => '0');
	signal PCM_static_to_BM_Left	: std_logic_vector(15 downto 0)	:= (others => '0');
	signal PCM_static_to_BM_Right	: std_logic_vector(15 downto 0)	:= (others => '0');
	signal PCM_BM_to_static_Left	: std_logic_vector(15 downto 0)	:= (others => '0');
	signal PCM_BM_to_static_Right	: std_logic_vector(15 downto 0)	:= (others => '0');
	
	signal PCM_control_PR_to_BM			: std_logic_vector(3 downto 0)	:= (others => '0');
	signal PCM_control_BM_to_PR			: std_logic_vector(7 downto 0)	:= (others => '0');
	signal PCM_control_static_to_BM	: std_logic_vector(7 downto 0)	:= (others => '0');
	signal PCM_control_BM_to_static	: std_logic_vector(3 downto 0)	:= (others => '0');
	
	signal PCM_reset_BM_to_PR			: std_logic	:= '0';
	signal PCM_clock_BM_to_PR			: std_logic	:= '0';
	signal PCM_clk_48k_BM_to_PR		: std_logic	:= '0';
	
	signal fft_PR_to_BM_re			: std_logic_vector(23 downto 0)	:= (others => '0');
	signal fft_PR_to_BM_im			: std_logic_vector(23 downto 0)	:= (others => '0');
	signal fft_BM_to_PR_re			: std_logic_vector(23 downto 0)	:= (others => '0');
	signal fft_BM_to_PR_im			: std_logic_vector(23 downto 0)	:= (others => '0');
	signal fft_static_to_BM_re		: std_logic_vector(23 downto 0)	:= (others => '0');
	signal fft_static_to_BM_im		: std_logic_vector(23 downto 0)	:= (others => '0');
	signal fft_BM_to_static_re		: std_logic_vector(23 downto 0)	:= (others => '0');
	signal fft_BM_to_static_im		: std_logic_vector(23 downto 0)	:= (others => '0');
	
	signal fft_control_PR_to_BM		: std_logic_vector(3 downto 0)	:= (others => '0');
	signal fft_control_BM_to_PR		: std_logic_vector(15 downto 0)	:= (others => '0');
	signal fft_control_static_to_BM	: std_logic_vector(15 downto 0)	:= (others => '0');
	signal fft_control_BM_to_static	: std_logic_vector(3 downto 0)	:= (others => '0');
		
	signal fft_reset_BM_to_PR			: std_logic	:= '0';
	signal fft_clock_BM_to_PR			: std_logic	:= '0';
	signal fft_clock_48k_BM_to_PR		: std_logic	:= '0';
	signal BM_enable						: std_logic := '1';
	
	signal ac97_sync_i				: std_logic	:= '0';
	signal done_i						: std_logic	:= '0';
	signal clk_48k						: std_logic	:= '0';
	signal clk_48k_i					: std_logic	:= '0';
	signal locked_48k					: std_logic := '0';
	signal ok_48k						: std_logic := '0';
	
	signal forward_fft_input		: std_logic_vector(23 downto 0)	:= (others => '0');
	
	signal sample_number				: std_logic_vector(7 downto 0)	:= (others => '0');
	
	signal clk_40M						: std_logic := '0';
	signal clk_40M_i					: std_logic := '0';
	signal locked_40M					: std_logic := '0';
	
	signal fft_data_right_sel		: std_logic_vector(23 downto 0)	:= (others => '0');
	signal fft_data_left_sel		: std_logic_vector(23 downto 0)	:= (others => '0');
	signal mux_select					: std_logic := '0';
	
	signal PCM_output_right			: std_logic_vector(15 downto 0)	:= (others => '0');
	signal PCM_output_left			: std_logic_vector(15 downto 0)	:= (others => '0');
	
	signal PCM_fft_to_vga_re		: std_logic_vector(23 downto 0) := (others => '0');
	signal PCM_fft_to_vga_im		: std_logic_vector(23 downto 0) := (others => '0');
	signal fft_static_input			: std_logic_vector(23 downto 0) := (others => '0');
begin
	
	buf_100M: BUFG port map(	I => clk,
										O => clk_100M);
	--clk_100M <= clk;
	
	--PCM_control_static_to_BM(7 downto 4) 	<= not('1' & '1' & PB_RIGHT & PB_UP);
	--PCM_control_static_to_BM(3 downto 1)	<= "000";
	--PCM_control_static_to_BM(0) 				<= not(PB_LEFT);						--enable
	
	mux_select							<= '1';									--PINNED
	
	LED_0									<= not key_debug(0);
	LED_1									<= not key_debug(1);
	LED_2									<= not locked_48k;
	LED_3									<= not locked_40M;
	
	Debug									<= fft_control_BM_to_static(0) & PCM_control_BM_to_static(0) & "00";
	
	sync 									<= ac97_sync_i;
	
	hard_reset_n						<= not(hard_reset);
		
	--MUX output signals
	PCM_output_left	<= PCM_BM_to_static_Left	when mux_select = '1' else fft_data_left_sel(15 downto 0);
	PCM_output_right	<= PCM_BM_to_static_Right	when mux_select = '1' else fft_data_right_sel(15 downto 0);
	
	reset_unit: reset_module port map(	reset_button	=> reset_button,
													locked_48k		=> locked_48k,
													locked_40M		=> locked_40M,
													reset				=> reset,
													hard_reset		=> hard_reset
													);
	
	clk_gen_48k: generate_48k_clk port map( 	AC97_Bit_Clk 	=> AC97Clk,
															reset				=> hard_reset,
															sync				=> ac97_sync_i,
															clk_48k			=> clk_48k_i,
															locked_48k		=> locked_48k,
															status			=> ok_48k
															);
	
	buf_48k: BUFG port map(		I => clk_48k_i,
										O => clk_48k);
	--clk_48k <= clk_48k_i;
	
	Inst_DCM: DCM_40 PORT MAP(	CLKIN_IN => clk,
										RST_IN => hard_reset_n,
										CLKFX_OUT => clk_40M_i,
										CLK0_OUT	=> open,
										LOCKED_OUT => locked_40M
										);
	
	buf_40M: BUFG port map(		I => clk_40M_i,
										O => clk_40M);
	--clk_40M <= clk_40M_i;
												
	static_0: keyboard_control port map ( 	clk 				=> clk_100M,
														reset 			=> reset,

														KBD_CLOCK		=> KBD_CLOCK,
														KBD_DATA			=> KBD_DATA,
														
														debug				=> key_debug,
														
														key_out			=> key_out,
														key_valid		=> key_valid,
														
														main_control	=> main_control_keyboard,
														time_control	=> PCM_control_static_to_BM,
														freq_control	=> fft_control_keyboard);
	
	static_1: ac97_if port map(	ClkIn 					=> clk_100M,
											Reset 					=> hard_reset,
				 
											PCM_Playback_Left 	=> PCM_output_left,
											PCM_Playback_Right 	=> PCM_output_right,
											PCM_Playback_Accept 	=> open,
				 
											PCM_Record_Left 		=> PCM_static_to_BM_Left,
											PCM_Record_Right 		=> PCM_static_to_BM_Right,
											PCM_Record_Valid 		=> open,
			
											Debug 					=> open,
											LED_0 					=> open,
											LED_1 					=> open,
											LED_2 					=> open,
											LED_3 					=> open,
				 
											AC97reset_n 			=> AC97reset_n,
											AC97Clk 					=> AC97Clk,
											Sync 						=> ac97_sync_i,
											SData_Out 				=> SData_Out,
											SData_In 				=> SData_In
											);
	
	--we need to sign extend the input vector
	forward_fft_input <= sxt(PCM_BM_to_static_left, 24);
	static_2a: full_fft port map(			clk_100M						=> clk_100M,
													clk_48k						=> clk_48k,
													reset							=> reset,
													 
													fwd_inv						=> '1',								--forward transform
													enable						=> '1',								--forward enabled by default
													
													x0_re							=> forward_fft_input,
													x0_im							=> (others => '0'),				--tie to zero
													
													y0_re							=> fft_static_to_BM_re,
													y0_im							=> fft_static_to_BM_im,
													
													done							=> done_i,
													sample_number				=> sample_number
													);
													
	
	fft_control_static_to_BM <= sample_number & done_i & fft_control_keyboard(6 downto 0);
	PR_freq_1: PRM_freq_1 port map(		clk_100M						=> fft_clock_BM_to_PR,
													clk_48k						=> fft_clock_48k_BM_to_PR,
													reset							=> fft_reset_BM_to_PR,
													
													control_in					=> fft_control_BM_to_PR,
													control_out					=> fft_control_PR_to_BM,
													
													fft_data_in_re				=> fft_BM_to_PR_re,
													fft_data_in_im				=> fft_BM_to_PR_im,
													fft_data_out_re			=> fft_PR_to_BM_re,
													fft_data_out_im			=> fft_PR_to_BM_im
													);
													
	
--	static_2b: full_fft port map(			clk_100M						=> clk_100M,
--													clk_48k						=> clk_48k,
--													reset							=> reset,
--													 
--													fwd_inv						=> '0',								--inverse transform
--													enable						=> done_i,
--													 
--													x0_re							=> fft_BM_to_static_re,
--													x0_im							=> fft_BM_to_static_im,
--													
--													y0_re							=> fft_data_left_sel,			--going to the output mux
--													y0_im							=> open,								--we don't care about imaginary output
--													
--													done							=> open,
--													sample_number				=> open								--this signal is of no more importance
--													);
	
	fft_static_input <= sxt(PCM_static_to_BM_Left, 24);
	static_2b: full_fft port map(			clk_100M						=> clk_100M,
													clk_48k						=> clk_48k,
													reset							=> reset,
													 
													fwd_inv						=> '1',								--forward transform
													enable						=> '1',								--enabled by default
													 
													x0_re							=> fft_static_input,
													x0_im							=> (others => '0'),
													
													y0_re							=> PCM_fft_to_vga_re,
													y0_im							=> PCM_fft_to_vga_im,
													
													done							=> open,
													sample_number				=> open								--this signal is of no more importance
													);
													
	static_3: VGA_controller port map(  clk_40M						=> clk_40M,
													clk_48k						=> clk_48k,
													reset 						=> reset,
													  
													time_control_out			=> PCM_control_BM_to_static,
													freq_control_out			=> fft_control_BM_to_static,
													main_control_in			=> main_control_keyboard,
													time_control_in			=> PCM_control_static_to_BM,
													freq_control_in			=> fft_control_keyboard,
													keyboard_control_data	=> key_out,
													keyboard_data_valid		=> key_valid,
													
													fft_data_re_in_left_0	=> fft_static_to_BM_re,
													fft_data_im_in_left_0	=> fft_static_to_BM_im,
													fft_data_re_in_left_1	=> fft_BM_to_static_re,
													fft_data_im_in_left_1	=> fft_BM_to_static_im,
													fft_data_re_in_left_2	=> PCM_fft_to_vga_re,
													fft_data_im_in_left_2	=> PCM_fft_to_vga_im,
													sample_number				=> sample_number(6 downto 0),
											
													VGA_OUT_RED 				=> VGA_OUT_RED,
													VGA_OUT_GREEN 				=> VGA_OUT_GREEN,
													VGA_OUT_BLUE 				=> VGA_OUT_BLUE,
													VGA_OUT_PIXEL_CLOCK 		=> VGA_OUT_PIXEL_CLOCK,
													VGA_COMP_SYNCH 			=> VGA_COMP_SYNCH,
													VGA_OUT_BLANK_Z 			=> VGA_OUT_BLANK_Z,
													VGA_HSYNCH 					=> VGA_HSYNCH,
													VGA_VSYNCH 					=> VGA_VSYNCH
													);
	 
	PR_time_1: PRM_time_1 port map(	clk 						=> PCM_clock_BM_to_PR,			--because of PlanAhead error, clock has been routed through BM
												clk_48k					=> PCM_clk_48k_BM_to_PR,
												reset 					=> PCM_reset_BM_to_PR,
			
												control_in 				=> PCM_control_BM_to_PR,
												control_out				=> PCM_control_PR_to_BM,
			
												PCM_data_in_right 	=> PCM_BM_to_PR_Right,
												PCM_data_in_left 		=> PCM_BM_to_PR_Left,
												PCM_data_out_right 	=> PCM_PR_to_BM_Right,
												PCM_data_out_left 	=> PCM_PR_to_BM_Left
												);
	
	--TO/FROM TIME DOMAIN
	PCM_BM_PR_to_static_Right_1: busmacro_xc2vp_l2r_async_enable_narrow port map(
										input0 					=> PCM_PR_to_BM_Right(0),
										input1 					=> PCM_PR_to_BM_Right(1),
										input2 					=> PCM_PR_to_BM_Right(2),
										input3 					=> PCM_PR_to_BM_Right(3),
										input4 					=> PCM_PR_to_BM_Right(4),
										input5 					=> PCM_PR_to_BM_Right(5),
										input6 					=> PCM_PR_to_BM_Right(6),
										input7 					=> PCM_PR_to_BM_Right(7),
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0					=> PCM_BM_to_static_Right(0),
										output1					=> PCM_BM_to_static_Right(1),
										output2					=> PCM_BM_to_static_Right(2),
										output3					=> PCM_BM_to_static_Right(3),
										output4					=> PCM_BM_to_static_Right(4),
										output5					=> PCM_BM_to_static_Right(5),
										output6					=> PCM_BM_to_static_Right(6),
										output7					=> PCM_BM_to_static_Right(7)
										);
										
	PCM_BM_PR_to_static_Right_2: busmacro_xc2vp_l2r_async_enable_narrow port map(
										input0 					=> PCM_PR_to_BM_Right(8),
										input1 					=> PCM_PR_to_BM_Right(9),
										input2 					=> PCM_PR_to_BM_Right(10),
										input3 					=> PCM_PR_to_BM_Right(11),
										input4 					=> PCM_PR_to_BM_Right(12),
										input5 					=> PCM_PR_to_BM_Right(13),
										input6 					=> PCM_PR_to_BM_Right(14),
										input7 					=> PCM_PR_to_BM_Right(15),
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0					=> PCM_BM_to_static_Right(8),
										output1					=> PCM_BM_to_static_Right(9),
										output2					=> PCM_BM_to_static_Right(10),
										output3					=> PCM_BM_to_static_Right(11),
										output4					=> PCM_BM_to_static_Right(12),
										output5					=> PCM_BM_to_static_Right(13),
										output6					=> PCM_BM_to_static_Right(14),
										output7					=> PCM_BM_to_static_Right(15)
										);
										
	PCM_BM_PR_to_static_Left_1: busmacro_xc2vp_l2r_async_enable_narrow port map(
										input0 					=> PCM_PR_to_BM_Left(0),
										input1 					=> PCM_PR_to_BM_Left(1),
										input2 					=> PCM_PR_to_BM_Left(2),
										input3 					=> PCM_PR_to_BM_Left(3),
										input4 					=> PCM_PR_to_BM_Left(4),
										input5 					=> PCM_PR_to_BM_Left(5),
										input6 					=> PCM_PR_to_BM_Left(6),
										input7 					=> PCM_PR_to_BM_Left(7),
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0					=> PCM_BM_to_static_Left(0),
										output1					=> PCM_BM_to_static_Left(1),
										output2					=> PCM_BM_to_static_Left(2),
										output3					=> PCM_BM_to_static_Left(3),
										output4					=> PCM_BM_to_static_Left(4),
										output5					=> PCM_BM_to_static_Left(5),
										output6					=> PCM_BM_to_static_Left(6),
										output7					=> PCM_BM_to_static_Left(7)
										);
										
	PCM_BM_PR_to_static_Left_2: busmacro_xc2vp_l2r_async_enable_narrow port map(
										input0 					=> PCM_PR_to_BM_Left(8),
										input1 					=> PCM_PR_to_BM_Left(9),
										input2 					=> PCM_PR_to_BM_Left(10),
										input3 					=> PCM_PR_to_BM_Left(11),
										input4 					=> PCM_PR_to_BM_Left(12),
										input5 					=> PCM_PR_to_BM_Left(13),
										input6 					=> PCM_PR_to_BM_Left(14),
										input7 					=> PCM_PR_to_BM_Left(15),
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0					=> PCM_BM_to_static_Left(8),
										output1					=> PCM_BM_to_static_Left(9),
										output2					=> PCM_BM_to_static_Left(10),
										output3					=> PCM_BM_to_static_Left(11),
										output4					=> PCM_BM_to_static_Left(12),
										output5					=> PCM_BM_to_static_Left(13),
										output6					=> PCM_BM_to_static_Left(14),
										output7					=> PCM_BM_to_static_Left(15)
										);
	
	PCM_BM_static_to_PR_Right_1: busmacro_xc2vp_r2l_async_enable_narrow port map(
										input0					=> PCM_static_to_BM_Right(0),
										input1					=> PCM_static_to_BM_Right(1),
										input2					=> PCM_static_to_BM_Right(2),
										input3					=> PCM_static_to_BM_Right(3),
										input4					=> PCM_static_to_BM_Right(4),
										input5					=> PCM_static_to_BM_Right(5),
										input6					=> PCM_static_to_BM_Right(6),
										input7					=> PCM_static_to_BM_Right(7),
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0 					=> PCM_BM_to_PR_Right(0),
										output1 					=> PCM_BM_to_PR_Right(1),
										output2 					=> PCM_BM_to_PR_Right(2),
										output3 					=> PCM_BM_to_PR_Right(3),
										output4 					=> PCM_BM_to_PR_Right(4),
										output5 					=> PCM_BM_to_PR_Right(5),
										output6 					=> PCM_BM_to_PR_Right(6),
										output7 					=> PCM_BM_to_PR_Right(7)										
										);
										
	PCM_BM_static_to_PR_Right_2: busmacro_xc2vp_r2l_async_enable_narrow port map(
										input0					=> PCM_static_to_BM_Right(8),
										input1					=> PCM_static_to_BM_Right(9),
										input2					=> PCM_static_to_BM_Right(10),
										input3					=> PCM_static_to_BM_Right(11),
										input4					=> PCM_static_to_BM_Right(12),
										input5					=> PCM_static_to_BM_Right(13),
										input6					=> PCM_static_to_BM_Right(14),
										input7					=> PCM_static_to_BM_Right(15),
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0 					=> PCM_BM_to_PR_Right(8),
										output1 					=> PCM_BM_to_PR_Right(9),
										output2 					=> PCM_BM_to_PR_Right(10),
										output3 					=> PCM_BM_to_PR_Right(11),
										output4 					=> PCM_BM_to_PR_Right(12),
										output5 					=> PCM_BM_to_PR_Right(13),
										output6 					=> PCM_BM_to_PR_Right(14),
										output7 					=> PCM_BM_to_PR_Right(15)										
										);
										
	PCM_BM_static_to_PR_Left_1: busmacro_xc2vp_r2l_async_enable_narrow port map(
										input0					=> PCM_static_to_BM_Left(0),
										input1					=> PCM_static_to_BM_Left(1),
										input2					=> PCM_static_to_BM_Left(2),
										input3					=> PCM_static_to_BM_Left(3),
										input4					=> PCM_static_to_BM_Left(4),
										input5					=> PCM_static_to_BM_Left(5),
										input6					=> PCM_static_to_BM_Left(6),
										input7					=> PCM_static_to_BM_Left(7),
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0 					=> PCM_BM_to_PR_Left(0),
										output1 					=> PCM_BM_to_PR_Left(1),
										output2 					=> PCM_BM_to_PR_Left(2),
										output3 					=> PCM_BM_to_PR_Left(3),
										output4 					=> PCM_BM_to_PR_Left(4),
										output5 					=> PCM_BM_to_PR_Left(5),
										output6 					=> PCM_BM_to_PR_Left(6),
										output7 					=> PCM_BM_to_PR_Left(7)								
										);
										
	PCM_BM_static_to_PR_Left_2: busmacro_xc2vp_r2l_async_enable_narrow port map(
										input0					=> PCM_static_to_BM_Left(8),
										input1					=> PCM_static_to_BM_Left(9),
										input2					=> PCM_static_to_BM_Left(10),
										input3					=> PCM_static_to_BM_Left(11),
										input4					=> PCM_static_to_BM_Left(12),
										input5					=> PCM_static_to_BM_Left(13),
										input6					=> PCM_static_to_BM_Left(14),
										input7					=> PCM_static_to_BM_Left(15),
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0 					=> PCM_BM_to_PR_Left(8),
										output1 					=> PCM_BM_to_PR_Left(9),
										output2 					=> PCM_BM_to_PR_Left(10),
										output3 					=> PCM_BM_to_PR_Left(11),
										output4 					=> PCM_BM_to_PR_Left(12),
										output5 					=> PCM_BM_to_PR_Left(13),
										output6 					=> PCM_BM_to_PR_Left(14),
										output7 					=> PCM_BM_to_PR_Left(15)										
										);
	
	PCM_BM_PR_to_static_control: busmacro_xc2vp_l2r_async_enable_narrow port map(
										input0					=> PCM_control_PR_to_BM(0),
										input1					=> PCM_control_PR_to_BM(1),
										input2					=> PCM_control_PR_to_BM(2),
										input3					=> PCM_control_PR_to_BM(3),
										input4					=> '0',
										input5					=> '0',
										input6					=> '0',
										input7					=> '0',
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0 					=> PCM_control_BM_to_static(0),
										output1 					=> PCM_control_BM_to_static(1),
										output2 					=> PCM_control_BM_to_static(2),
										output3 					=> PCM_control_BM_to_static(3),
										output4					=> open,
										output5					=> open,
										output6					=> open,
										output7					=> open
										);
										
	PCM_BM_static_to_PR_control: busmacro_xc2vp_r2l_async_enable_narrow port map(
										input0 					=> PCM_control_static_to_BM(0),
										input1 					=> PCM_control_static_to_BM(1),
										input2 					=> PCM_control_static_to_BM(2),
										input3 					=> PCM_control_static_to_BM(3),
										input4					=> PCM_control_static_to_BM(4),
										input5					=> PCM_control_static_to_BM(5),
										input6					=> PCM_control_static_to_BM(6),
										input7					=> PCM_control_static_to_BM(7),
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0					=> PCM_control_BM_to_PR(0),
										output1					=> PCM_control_BM_to_PR(1),
										output2					=> PCM_control_BM_to_PR(2),
										output3					=> PCM_control_BM_to_PR(3),
										output4					=> PCM_control_BM_to_PR(4),
										output5					=> PCM_control_BM_to_PR(5),
										output6					=> PCM_control_BM_to_PR(6),
										output7					=> PCM_control_BM_to_PR(7)										
										);
	
	PCM_clock_BM_to_PR 	<= clk_100M;
	PCM_clk_48k_BM_to_PR	<= clk_48k;
	PCM_BM_static_to_PR_clk_reset: busmacro_xc2vp_r2l_async_enable_narrow port map(
										input0					=> reset,
										input1					=> '0',--clk_100M,
										input2					=> '0',--clk_48k,
										input3					=> '0',
										input4					=> '0',
										input5					=> '0',
										input6					=> '0',
										input7					=> '0',
										enable0					=> BM_enable,
										enable1					=> BM_enable,
										enable2					=> BM_enable,
										enable3					=> BM_enable,
										enable4					=> BM_enable,
										enable5					=> BM_enable,
										enable6					=> BM_enable,
										enable7					=> BM_enable,
										output0 					=> PCM_reset_BM_to_PR,
										output1 					=> open,--PCM_clock_BM_to_PR,
										output2 					=> open,--PCM_clk_48k_BM_to_PR,
										output3 					=> open,
										output4					=> open,
										output5					=> open,
										output6					=> open,
										output7					=> open
										);
										
	--TO/FROM FREQUENCY DOMAIN
	fft_BM_to_static_re			<= fft_PR_to_BM_re;
	fft_BM_to_static_im			<= fft_PR_to_BM_im;
	fft_BM_to_PR_re				<= fft_static_to_BM_re;
	fft_BM_to_PR_im				<= fft_static_to_BM_im;
	fft_control_BM_to_static	<= fft_control_PR_to_BM;
	fft_control_BM_to_PR			<= fft_control_static_to_BM;									
	fft_clock_BM_to_PR			<= clk_100M;
	fft_clock_48k_BM_to_PR		<= clk_48k;
	fft_reset_BM_to_PR			<= reset;
										
end structural;
